(1) Field of the Invention
This invention relates generally to the field of integrated circuits fabrication, and more particularly, to a process of forming spin-on-glass (SOG) layer on a metal pattern to improve the surface planarization of the integrated circuits.
(2) Description of the Prior Art
In order to form compact and high density devices, multiple layers of conductors and insulators are stacked within the limited area in IC fabrication. It tends to have steep and complicated topography on the wafer surfaces. The mentioned scenario can be more caustic in the process of dynamic random access memory (DRAM) because the alternating multi-layers of polysilicon and dielectric layers are deposited and etched to form the capacitors. These complicated topography on wafer surfaces has severe negative effect on subsequent processes. It will diminish the range of depth of focus during lithography exposure especially and distort the photoresist profiles or even cause residue during etching, and it may produce undesired metal lines shorting. The planarization technologies of so-called "biased sputter oxide deposition" or "oxide reflow" are currently employed to solve the topography problem, however they are both time consuming and costly. U.S. Pat. No. 5,393,708 to Hsia et al. (the entire disclosure of which is herein incorporated by reference) describes another simple and low cost technique which is used spin-on-glass (SOG) for planarization as the dielectric interlayer material between two metal layers. SOGs often called organic silicates (a type of silicon dioxide), are applied in liquid form across the entire silicon wafer surface by spinning in the same manner as photoresist. The liquid silicate is then heated to convert it into a silica film. The liquid silicate easily flows into any dimensional valley at the upper surface of the silicon substrate to fill and thereby obtain planar topography. Therefore, SOG becomes most widely used planarization material for today's semiconductor industry. Common SOG materials include silicates or siloxane mixed in alcohol or ketone based solvents. Siloxane-based SOG materials have organic methyl (CH.sub.3) or phenyl (C.sub.6 H.sub.5) groups added to improve cracking resistance. However, non etching back (NEB) SOG planarization process suffers poison via due to outgassing from damaged SOG by O.sub.2 plasma treatment to strip photoresist layer. Therefore, partial etching back (PEB) or total etching back (TEB) become more popular techniques because of less SOG remained on metal pattern surface.
Referring now to FIGS. 1(a) to 1(c), there are cross sectional representations of the conventional SOG etching back process. First, metal patterns 3 which are composed of aluminum alloys 31 and titanium nitride (TiN) antireflective layer 32 are defined on a semiconductor substrate 1. Next, a liner 5 is deposited on the entire substrate surface. A SOG layer 7 is then directly coated over the liner 5 as shown in Fig. 1(a). In order to achieve more stable via RC time constant, PEB or TEB is performed to reduce the overall thickness of the SOG layer as shown in FIG. 1(b). However, due to nonuniform SOG thickness (center portion 7a is thicker than edges 7b), overetch is necessary to completely remove entire SOG layer. That causes so-called metal corner clipping as shown in FIG. 1(c) which undesirably increases the resistance of the metal patterns. Therefore, it degrades the performance and reliability of the integrated circuits.
This invention reveals an improved process of intermetal dielectric planarization, particularly for solving the SOG edge thinning problem.